Analysis of Snapback Phenomena in VDMOS Transistor having the High Second Breakdown Current : A High ESD Mechanism Analysis
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概要
- 論文の詳細を見る
- 2009-11-01
著者
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Maegawa Shigeto
Mixed Signal Device Technology Department Production And Technology Unit Renesas Technology Corporat
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Kuroi Takashi
Mixed Signal Device Technology Department Production And Technology Unit Renesas Technology Corporat
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HATASAKO Kenichi
Mixed Signal Device Technology Department, Production and Technology Unit, Renesas Technology Corpor
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YAMAMOTO Fumitoshi
Mixed Signal Device Technology Department, Production and Technology Unit, Renesas Technology Corpor
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UENISHI Akio
Mixed Signal Device Technology Department, Production and Technology Unit, Renesas Technology Corpor
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Uenishi Akio
Mixed Signal Device Technology Department Production And Technology Unit Renesas Technology Corporat
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Maegawa Shigeto
Mixed Signal Device Technology Department Devices & Analysis Technology Division Renesas Electro
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Hatasako Kenichi
Mixed Signal Device Technology Department Devices & Analysis Technology Division Renesas Electro
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Yamamoto Fumitoshi
Mixed Signal Device Technology Department Devices & Analysis Technology Division Renesas Electro
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Kuroi Takashi
Mixed Signal Device Technology Department Devices & Analysis Technology Division Renesas Electro
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Uenishi Akio
Mixed Signal Device Technology Department Devices & Analysis Technology Division Renesas Electro
関連論文
- Analysis of Snapback Phenomena in VDMOS Transistor having the High Second Breakdown Current : A High ESD Mechanism Analysis
- ESD Robustness Improvement for Integrated DMOS Transistors-The Different Gate-Voltage Dependence of I_ Between VDMOS and LDMOS Transistors
- Novel Design of Vertical Double-Diffused Metal–Oxide–Semiconductor Transistor for High Electrostatic Discharge Robustness