In-Depth Study of Two-Dimensional Layout Dependences in Multiple-Stressor CMOS for 45nm Technology Node High-Performance Applications

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概要

• 論文の詳細を見る
• 2007-09-19

著者

• MIYASHITA T.

  Fujitsu Laboratories Ltd.

• OWADA T.

  Fujitsu Limited

• SATOH S.

  Fujitsu Laboratories Ltd.

• Hatada A.

  Fujitsu Limited

• OGURA J.

  Fujitsu Limited

• SAKUMA T.

  Fujitsu Laboratories Ltd.

• NOMURA H.

  Fujitsu Limited

• MIYAOKA H.

  Fujitsu Limited

• HASEGAWA A.

  Fujitsu Limited

• YAMAGUCHI S.

  Fujitsu Limited

関連論文

• Technology Trend of Soft Errors based on Accurate Estimation Method
• Potential of and Issues with Multiple-Stressor Technology (MST) in High-Performance 45nm Generation Devices
• Advanced I/O Technology using Laterally Modulated Channel MOSFET for 65-nm Node SoC
• Optimization of Giga-bit DRAM Cell Transistors by Channel and Drain Engineering
• In-Depth Study of Two-Dimensional Layout Dependences in Multiple-Stressor CMOS for 45nm Technology Node High-Performance Applications

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