Empirical Quantitative Modeling of Threshold Voltage of Sub-50-nm Double-Gate SOI MOSFET's

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概要

• 論文の詳細を見る
• 2005-09-13

著者

• Tahara Yuki

  Dept. Of Electronics Kansai University

• Omura Yasuhisa

  Dept.of Electronics Kansai Univ.

• Omura Yasuhisa

  Dept. Of Electronics Kansai University

• Omura Yasuhisa

  Dept. Of Electronics Faculty Of Engineering Kansai University

関連論文

• Empirical Quantitative Modeling of Threshold Voltage of Sub-50-nm Double-Gate SOI MOSFET's
• Feasibility Study on Self-Collimated Light-Focusing Device Using 2-D Photonic Crystal with a Parallelogram Lattice
• Sub-100-nm Partial-Ground-Plane(PGP) Silicon-on-Insulator (SOI) MOSFET Structure for Radio-Frequency and Digital Applications
• A New Basic Element for Neural Logic Circuits

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