Improvement of Bit-Line Contact Resistance for Memory Devices with Silicide Gate
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概要
- 論文の詳細を見る
- 1997-09-16
著者
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CHOI Y.
DRAM PM Center, Samsung Electronics Co.
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Ryu B.
Dram Product Engineering Memory Business Samsung Electronics
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Choi Y.
Dram Pm Center Samsung Electronics Co.
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Choi Y.
Dram Product Engineering Memory Business Samsung Electronics
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KIM T.
DRAM Product Engineering, Memory Business, Samsung Electronics
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MOON C.
DRAM Product Engineering, Memory Business, Samsung Electronics
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KOH H.
DRAM Product Engineering, Memory Business, Samsung Electronics
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JIN J.
DRAM Product Engineering, Memory Business, Samsung Electronics
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Kim T.
Dram Product Engineering Memory Business Samsung Electronics
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Moon C.
Dram Product Engineering Memory Business Samsung Electronics
関連論文
- URCAT (U-shaped-Recess-Channel-Array Transistor) Technology for 60nm DRAM and beyond
- Cost-Effective and Highly Reliable 6F2 Multi-Gigabit DRAM in 60nm Technology Node for Low Power and High Performance Applications
- Improvement of Bit-Line Contact Resistance for Memory Devices with Silicide Gate