SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits(VLSI Design Technology and CAD)
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概要
- 論文の詳細を見る
In this paper, we present the condition for the effective wire addition in Look-Up-Table-based (LUT-based) field programmable gate array (FPGA) circuits, and an optimization procedure utilizing the effective wire addition. Each wire has different characteristics, such as delay and power dissipation. Therefore, the replacement of one critical wire for the circuit performance with many non-critical ones, i.e., many-addition-for-one-removal (m-for-1) is sufficiently useful. However, the conventional logic optimization methods based on sets of pairs of functions to be distinguished (SPFDs) for LUT-based FPGA circuits do not make use of the m-for-1 manipulation, and perform only simple replacement and removal, i.e., the one-addition-for-one-removal (1-for-1) manipulation and the no-addition-for-one-removal (0-for-1) manipulation, respectively. Since each LUT can realize an arbitrary internal function with respect to a specified number of input variables, there is no sufficient condition at the logic design level for simple wire addition. Moreover, in general, simple addition of a wire has no effects for removal of another wire, and it is important to derive the condition for non-simple and effective wire addition. We found the SPFD-based condition that wire addition is likely to make another wire redundant or replaceable, and developed an optimization procedure utilizing this effective wire addition. According to the experimental results, when we focused on the delay reduction of LUT-based FPGA circuits, our method reduced the delay by 24.2% from the initial circuits, while the conventional SPFD-based logic optimization and the enhanced global rewiring reduced it by 14.2% and 18.0%, respectively. Thus, our method presented in this paper is sufficiently practical, and is expected to improve the circuit performance.
- 社団法人電子情報通信学会の論文
- 2005-04-01
著者
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YAMASHITA SHIGERU
Graduate School of Information Science, Nara Institute of Science and Technology
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Yamashita Shigeru
Nara Inst. Sci. And Technol. Ikoma‐shi Jpn
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TANAKA Katsunori
Graduate School of Informatics, Kyoto University
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YAMASHITA Shigeru
Ritsumeikan University
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Yamashita Shigeru
Graduate School Of Information Science Nara Institute Of Science And Technology
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Tanaka Katsunori
Graduate School Of Informatics Kyoto University
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