Secure Processor Architecture for High-Speed Verification of Memory Integrity
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概要
- 論文の詳細を見る
This paper proposes a processor-integrated approach to verify the data integrity of external memory. Present processors always trust the data in off-chip memory without question. However, assuring the data integrity of external memory will be one of the important basic technologies in secure computing environments in the future. A processor with the proposed mechanism can guarantee the integrity against memory corruption even when running malicious software (e.g., computer viruses, corrupted untrusted operating systems) or when subject to physical attacks. Many software verification methods have been proposed. However, those methods have limitations in speed and security in comparison with hardware-integrated approaches. A processor architecture that uses an "Incremental Multiset Hash Function" has also been proposed by G.E. Shu et al. However it degrades the processor speed due to its heavy use of hash operations. Our architecture achieves high-speed verification of memory integrity using a hardware accelerator that monitors the behavior of memory accesses. By using a complicated but computationally lightweight scheme to count memory accesses, the architectures can use Rijndael symmetric key cryptography, which is a superset of AES and has fast implementations, instead of a computationally expensive hash function. That contributes to high-speed operation of integrity verification. The speed was evaluated by using SimpleScalar. The instructions per cycle of our architecture were consistently better than in previous approaches, and improved by 60% for high cache miss rates.
- 一般社団法人情報処理学会の論文
- 2006-11-28
著者
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YAMASHITA SHIGERU
Nara Institute of Science and Technology
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Yamashita Shigeru
Nara Inst. Sci. And Technol. Ikoma‐shi Jpn
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Nakanishi Masaki
Nara Inst. Sci. And Technol. Ikoma‐shi Jpn
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OKAZAKI ATSUYA
IBM Research, Tokyo Research Laboratory
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Okazaki Atsuya
Ibm Research Tokyo Research Laboratory
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