A Physical Model for Hole Direct Tunneling Currents Through Ultrathin Gate Dielectrics in Advanced CMOS Devices
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概要
- 論文の詳細を見る
- 2001-09-25
著者
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Li M.
Silicon Nano Device Lab (sndl) Ece Department National University Of Singapore
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Li M.
Silicon Nano Device Lab Department Of Electrical & Computer Engineering National University Of S
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HOU Y.
Silicon Nano Device Lab (SNDL), ECE Department, National University of Singapore
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LAI W.
Silicon Nano Device Lab, Department of Electrical & Computer Engineering National University of Sing
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JIN Y.
Chartered Semiconductor Manufacturing Ltd
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Lai W.
Silicon Nano Device Lab Department Of Electrical & Computer Engineering National University Of S
関連論文
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- A Physical Model for Hole Direct Tunneling Currents Through Ultrathin Gate Dielectrics in Advanced CMOS Devices