65nm Device Manufacture Using Shaped E-Beam Lithography
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2004-06-30
著者
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Leverd Francois
Stmicroelectronics
-
Henry Daniel
Stmicroelectronics
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Judong Fabienne
Stmicroelectronics
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Palla Ramiro
Stmicroelectronics
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Broekaart Marcel
Philips Semiconductors
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PAIN Laurent
CEA-LETI/Grenoble
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JURDIT Murielle
CEA-LETI/Grenoble
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LAPLANCHE Yves
STMicroelectronics
-
TODESCHINI Jerome
PHILIPS Semiconductors
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LEININGER Hugues
STMicroelectronics
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TOURNIOL Sonia
STMicroelectronics
-
FAURE Romuald
STMicroelectronics
-
BOSSY Xavier
STMicroelectronics
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BEVERINA Alessio
STMicroelectronics
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BROSSELIN Karine
STMicroelectronics
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DEPOYAN Linda
STMicroelectronics
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FRIEC Yannick
STMicroelectronics
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JONGHE Veronique
PHILIPS Semiconductors
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JOSSE Emmanuelle
STMicroelectronics
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HINSINGER Olivier
STMicroelectronics
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BRUN Philippe
CEA-LETI/Grenoble
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WOO Michael
MOTOROLA
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STOLK Peter
PHILIPS Semiconductors
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TAVEL Brice
PHILIPS Semiconductors
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ARNAUD Franck
STMicroelectronics
関連論文
- 65nm Device Manufacture Using Shaped E-Beam Lithography
- Novel High-Performance Analog Devices for Advanced Low-Power High-$k$ Metal Gate Complementary Metal--Oxide--Semiconductor Technology
- 65 nm Device Manufacture Using Shaped E-Beam Lithography