スポンサーリンク
ULSI Laboratory of LG Semicon Co. Ltd. | 論文
- W as a Bit Line Interconnection in Capacitor-Over-Bit-line (COB) Structured Dynamic Random Access Memory (DRAM) and Feasible Diffusion Barrier Layer
- Reduction of junction leakage current and sheet resistance using C-49 TiSi_2 as a diffusion source
- Reduction of junction leakage current and sheet resistance using C-49 TiSi_2 as a diffusion source
- Formation of Low-Resistivity Gate Electrode Suitable for the Future Devices Using Clustered DCS-Wsix Polycide
- Structural Evaluation of CVD WSix and Its Effect on Polycide Line Resistance
- W as a BIT Line Interconnection in COB Structured DRAM and Feasible Diffusion Barrier Layer
- Electrical Characteristics of Ultra Short Channel CMOS Device for Giga-bit DRAM Applications
- Effect of Nitride Sidewall Spacer on Hot Carrier Reliability Characteristics of MOSFET's