スポンサーリンク
PHILIPS Semiconductors | 論文
- Highly scalable and WF-tunable Ni(Pt)Si / SiON TOSI-gate CMOS devices obtained in a CMP-less integration scheme
- Effect of Process Induced Strain in 35nm FDSOI Devices with Ultra-Thin Silicon Channels
- 65nm Device Manufacture Using Shaped E-Beam Lithography
- Improvement of Bulk CMOS Electrostatic Integrity using Germanium and Carbon co-implantation
- Using MASTAR as a Pre-SPICE Model Generator for Early Technology Assessment and Circuit Simulation
- 45nm Conventional Bulk and "Bulk+" Architectures for Low-Cost GP/LP Applications
- A Full Analytical Model to evaluate Strain Induced by CESL on MOSFET Performances
- Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels
- 65 nm Device Manufacture Using Shaped E-Beam Lithography