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Korea Institute for Advanced Study, 207-43 Cheongryangri, Seoul, Korea | 論文
- Design Technique for Ramped Gate Soft-Programming in Over-Erased NOR Type Flash EEPROM Cells
- Spatial and Temporal Characterization of Programming Charge in SONOS Memory Cell: Effects of Localized Electron Trapping
- High Speed, Low Power Programming in 0.17μm Channel Length NOR-type Floating Gate Flash Memory Cell Free of Drain Turn-On Effects