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Ips Waseda University | 論文
- Inter search mode reduction based parallel propagate partial SAD architecture for variable block size motion estimation in H.264/AVC (第20回 回路とシステム軽井沢ワークショップ論文集) -- (映像応用)
- Constant Bit-Rate Multi-Stage Rate Control for Rate-Distortion Optimized H.264/AVC Encoders
- A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule
- A-4-33 High Throughput Rate-1/2 Partially-Parallel Irregular LDPC Decoder
- Loss free VLSI oriented full computation reusing algorithm for H.264 fractional motion estimation (映像信号処理)
- An Ultra-Low Bandwidth Design Method for MPEG-2 to H.264/AVC Transcoding
- Homogeneity Based Image Objective Quality Metric(Image Processing and Video Processing)
- A-6-12 Prediction-based Center-bias Fast Fractional Motion Estimation Algorithm for H.264/AVC
- Multi-objective Job Shop Rescheduling with Evolutionary Algorithm
- Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC
- Highly Parallel and Fully Reused H.264/AVC High Profile Intra Predictor Generation Engine for Super Hi-Vision 4k×4k@60fps
- A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction
- Fast H.264/AVC DIRECT Mode Decision Based on Mode Selection and Predicted Rate-Distortion Cost
- Content Based Coarse to Fine Adaptive Interpolation Filter for High Resolution Video Coding
- Low-Complexity Coarse-Level Mode-Mapping Based H.264/AVC to H.264/SVC Spatial Transcoding for Video Conferencing