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Ips Waseda University | 論文
- Low-Complex Equalization for Single Carrier Systems Employing Cyclic Prefix over Time-Variant Channels(Wireless Communication Technologies)
- Standard Deviation and Intra Prediction Mode Based Adaptive Spatial Error Concealment (SEC) in H.264/AVC
- Variable Block Size Motion Vector Retrieval Schemes for H.264 Inter Frame Error Concealment
- Highly Parallel Fractional Motion Estimation Engine for Super Hi-Vision 4k×4k@60fps
- A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder
- A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
- A High-Speed Design of Montgomery Multiplier
- Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm
- An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard
- High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding
- Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application
- Hardware-Oriented Early Detection Algorithms for 4×4 and 8×8 All-Zero Blocks in H.264
- VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis
- Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation
- Macroblock and Motion Feature Analysis to H.264/AVC Fast Inter Mode Decision
- Adaptive Search Range Algorithms for Variable Block Size Motion Estimation in H.264/AVC
- Content-Aware Fast Motion Estimation for H.264/AVC
- Edge Block Detection and Motion Vector Information Based Fast VBSME Algorithm
- Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC
- A-4-18 Integer Search Position Based Fast Motion Estimation in H.264/AVC