スポンサーリンク
IPS, Waseda University | 論文
- An efficient encryption scheme for H.264 format video streams (第20回 回路とシステム軽井沢ワークショップ論文集) -- (画像応用)
- A high-speed design of Montgomery multiplier (第20回 回路とシステム軽井沢ワークショップ論文集) -- (システム実現技術)
- Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
- A 41mW VGA【triple bond】fps Quadtree Video Encoder for Video Surveillance Systems
- Variable Block Size Motion Vector Retrieval Schemes for H.264 Inter Frame Error Concealment
- Highly Parallel Fractional Motion Estimation Engine for Super Hi-Vision 4k×4k@60fps
- A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder
- A High-Speed Design of Montgomery Multiplier
- Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm
- An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard
- Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application
- Hardware-Oriented Early Detection Algorithms for 4×4 and 8×8 All-Zero Blocks in H.264
- VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis
- Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation
- Macroblock and Motion Feature Analysis to H.264/AVC Fast Inter Mode Decision
- Edge Block Detection and Motion Vector Information Based Fast VBSME Algorithm
- Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC
- A-4-18 Integer Search Position Based Fast Motion Estimation in H.264/AVC
- Inter search mode reduction based parallel propagate partial SAD architecture for variable block size motion estimation in H.264/AVC (第20回 回路とシステム軽井沢ワークショップ論文集) -- (映像応用)
- Constant Bit-Rate Multi-Stage Rate Control for Rate-Distortion Optimized H.264/AVC Encoders