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Fujitsu Laboratories Ltd., Akiruno Technology Center, 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan | 論文

• Simple Modeling and Characterization of Stress Migration Phenomena in Cu Interconnects
• Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Vias on Bumpless Wafer-on-Wafer Technology
• Novel Through Silicon Vias Leakage Current Evaluation Using Infrared-Optical Beam Irradiation
• Characterization of Local Strain around Through-Silicon Via Interconnects by Using X-ray Microdiffraction
• Impact of Thermomechanical Stresses on Bumpless Chip in Stacked Wafer Structure
• Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration

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