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Dept. of Semiconductor Science, Dongguk University | 論文
- DESIGN OF A NOVEL LOGARITHMIC AMPLIFIER WITH A TWO-STEP LINEAR LIMIITING TECHNIQUE
- DESIGN OF A NOVEL LOGARITHMIC AMPLIFIER WITH A TWO-STEP LINEAR LIMIITING TECHNIQUE
- AN 8-BIT 500MSPS CMOS A/D CONVERTER WITH A NOVEL ANALOG DYNAMIC LATCH(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- AN 8-BIT 500MSPS CMOS A/D CONVERTER WITH A NOVEL ANALOG DYNAMIC LATCH(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- DESIGN OF A 3V 6-BIT 900MSPS CMOS A/D CONVERTER WITH AN IMPROVED DYNAMIC LATCH
- DESIGN OF A 3V 6-BIT 900MSPS CMOS A/D CONVERTER WITH AN IMPROVED DYNAMIC LATCH