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Department of Computer Science and Engineering, Waseda University | 論文
- A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures
- A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit
- Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures
- A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution
- An Extensible Secure OS Architecture for Embedded Systems (Preprint)
- A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution
- Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling
- Analyzing Spatial Structure of IP Addresses for Detecting Malicious Websites
- Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems
- A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation
- Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design
- Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages
- An Extensible Secure OS Architecture for Embedded Systems
- An Extensible Secure OS Architecture for Embedded Systems
- Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling
- Influence of Organizational Change on Product Metrics and Defects
- BS-1-60 A New Learning Mechanism of Forwarding Information Base in CCN
- A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures