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Department of Computer Science, Waseda University | 論文
- A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit
- Scan Vulnerability in Elliptic Curve Cryptosystems
- Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule(VLSI Architecture,VLSI Design and CAD Algorithms)
- FPGA-Based Reconfigurable Adaptive FEC(System Level Design)(VLSI Design and CAD Algorithms)
- New Attachment to Periodontally Diseased Root Surfaces Treated with Hydrochloric Acid
- C-5 Interfacial Structure between Implant Materials and Periodontal Tissue in the Rat
- Cell-bound Pullulanase from Streptomyces sp. No.27
- Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
- A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
- A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
- A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems
- Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
- Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions(Design Methodology)(VLSI Design and CAD Algorithms)
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions(Simulation Acceletor)(VLSI Design and CAD Algorithms)
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
- A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories
- A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation(Special Section on VLSI Design and CAD Algorithms)