スポンサーリンク

Department Of Electronic Engineering Faculty Of Engineering University Of Tokyo:(present Address) Re | 論文

• Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells(Circuit Synthesis, VLSI Design and CAD Algorithms)
• Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization(VLSI Design Technology and CAD)
• High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability(Physical Design)(VLSI Design and CAD Algorithms)
• Calculations of Energy Levels of Oxygen and Silicon Vacancies at the Si-SiO_2 Interface
• Magnetic and Electrical Properties of Vacuum-Deposited CdCr_2Se_4 Thin Film

スポンサーリンク