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Department Of Electrical And Semiconductor Engineering Chonnam National University | 論文

• Layout Dependent Induced Leakage and its Prevention with Different Shallow Trench Isolation Schemes in 0.18μm Dual Gate Complementary Metal Oxide Semiconductor Technology
• Etch Defect Reduction Using SF_6/O_2 Plasma Cleaning and Optimizing Etching Recipe in Photo Resist Masked Gate Poly Silicon Etch Process
• Shallow Trench Isolation Top Corner Rounding Using Si Soft Etching Following Diluted Hydrofluorine Solution

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