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Department Of Computer Science Waseda University | 論文
- A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation(Special Section on VLSI Design and CAD Algorithms)
- An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation(Special Section on VLSI Design and CAD Algorithms)
- C-5 A Software/Hardware Codesign for MPEG Encoder
- High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
- A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files(Special Section on VLSI Design and CAD Algorithms)
- Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores(Special Section on VLSI Design and CAD Algorithms)
- An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares (Special Section on Discrete Mathematics and Its Applications)
- CAM Processor Synthesis Based on Behavioral Descriptions (Special Section on VLSI Design and CAD Algorithms)
- A Hardware / Software Cosynthesis System for Digital Signal Processor Cores with Two Types of Register Files (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa)
- Synthesis of N-Acetyl-3-fluoro-neuraminic Acids(Organic Chemistry)
- Ears of the Robot : Direction of Arrival Estimation Based on Pattern Recognition Using Robot-Mounted Microphones
- A Two-Level Cache Design Space Exploration System for Embedded Applications
- An L1 Cache Design Space Exploration System for Embedded Applications
- A PRELIMINARY REPORT ON PHENOLOGICAL MONITORING USING EXPERIMENTAL CHAMBERS IN MT. KISOKOMAGATAKE, CENTRAL JAPAN (18th Symposium on Polar Biology)
- Multi-Cycle Path Detection Based on Propositional Satisfiability with CNF Simplification Using Adaptive Variable Insertion (Special Section on VLSI Design and CAD Algorithms)
- Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis(Logic and High Synthesis)(VLSI Design and CAD Algorithms)
- Look Up Table Compaction Based on Folding of Logic Functions(Special Section on VLSI Design and CAD Algorithms)
- A comparative study of most suitable miniplate fixation for mandibular symphysis fracture using a finite element model
- A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation(Timing Verification and Test Generation)(VLSI Design and CAD Algorithms)
- A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation