Yasumoto Kiyotoshi | Faculty of Information Engineering, Fukuoka Institute of Technology
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Faculty of Information Engineering, Fukuoka Institute of Technology | 論文
- A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI(Semiconductor Materials and Devices)
- 0.3-1.5V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier(Memory, Low-Power LSI and Low-Power IP)
- An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI's(Special Issue on the 1994 VLSI Circuits Symposium)
- A Low Power Bus Architecture with Local and Global Charge-Recycling Bus Techniques for Battery-Operated Ultra-High Data Rate ULSI's
- High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM (Special Section on High Speed and High Density Multi Functional LSI Memories)