LEE J. | Department of Electrical Engineering, KAIST
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概要
Department of Electrical Engineering, KAIST | 論文
- Synthesis of wafer scale graphene layer for future electronic devices(Session 2B : Graphene and III-Vs)
- Synthesis of wafer scale graphene layer for future electronic devices(Session 2B : Graphene and III-Vs)
- Improvement of Charge Retention in Flash Memory Devices by Very Light Doping of Lanthanum into an Aluminum-Oxide Blocking Layer
- Highly Reliable Interpoly Oxide Using ECR N_2O-Plasma for Next Generation Flash Memory
- A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-μm CMOS