A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-μm CMOS
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概要
- 論文の詳細を見る
- 2009-04-01
著者
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LEE Joonhee
Department of Computer Science, Yonsei University
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Lee Joonhee
Department Of Computer Science Yonsei University
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Lee Joonhee
Department Of Electrical Engineering Kaist
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KIM Sungjun
System LSI Division, Samsung Electronics CO.
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JEON Sehyung
Department of Electrical Engineering, KAIST
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LEE Woojae
Department of Electrical Engineering, KAIST
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CHO SeongHwan
Department of Electrical Engineering, KAIST
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Lee Woojae
Department Of Electrical Engineering Kaist
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Kim Sungjun
System Lsi Division Samsung Electronics Co.
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Jeon Sehyung
Department Of Electrical Engineering Kaist
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Cho Seonghwan
Kaist Daejeon Kor
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Cho Seonghwan
Department Of Electrical Engineering Kaist
関連論文
- Wireless Quality Assessment Using RLP NAK Rate in CDMA2000 1X Networks(Network)
- A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-μm CMOS
- An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder