TANAKA Shigeto | Graduate School of E., E., and C. Eng., Chuo University
スポンサーリンク
概要
Graduate School of E., E., and C. Eng., Chuo University | 論文
- A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture(Analog Signal Processing)
- The Design of a 2.7V, 200MS/s, and 14-Bit CMOS D/A Converter with 63dB of SFDR Characteristics for the 90 MHz Output Signal
- The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25V of Output Voltage Using a Fractional V_ Amplification Scheme(Electronic Circuits)