MIURA Takayoshi | Research Dept. 1, Semiconductor Leading Edge Technologies (Selete), Inc.

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• MIURA Takayoshiの詳細を見る
• 同名の論文著者
• Research Dept. 1, Semiconductor Leading Edge Technologies (Selete), Inc.の論文著者

Research Dept. 1, Semiconductor Leading Edge Technologies (Selete), Inc. | 論文

• High Quality Hf-Silicate Gate Dielectrics Fabrication by Atomic Layer Deposition (ALD) Technology
• Ni-Salicided Poly-Si/poly-SiGe-Layered Gate Technology for 65-nm-node CMOSFETs
• Improvements of Electrical Properties with Reduced Transient-Enhanced-Diffusion for 65nm-node CMOS Technology using Flash Lamp Annealing
• Production-Worthy HfSiON Gate Dielectric Fabrication Enabling EOT Scalability Down to 0.86nm and Excellent Reliability by Polyatomic Layer Chemical Vapor Deposition Technique

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