SHIRAKO Jun | Department of Computer Science, Waseda University

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• Department of Computer Science, Waseda Universityの論文著者

Department of Computer Science, Waseda University | 論文

• A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit
• Scan Vulnerability in Elliptic Curve Cryptosystems
• Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule(VLSI Architecture,VLSI Design and CAD Algorithms)
• Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
• A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)

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