Hirose Hideo | Faculty of Computer Science and Systems Engineering, Kyushu Institute of Technology
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概要
Faculty of Computer Science and Systems Engineering, Kyushu Institute of Technology | 論文
- Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time(Dependable Computing)
- Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores(Dependable Computing)
- On Detection of Bridge Defects with Stuck-at Tests
- A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits
- A Novel ATPG Method for Capture Power Reduction during Scan Testing(Dependable Computing)