Nakamura Yoshihisa | Graduate School of Science and Engineering, Ehime University
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概要
Graduate School of Science and Engineering, Ehime University | 論文
- Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
- Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
- Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors
- Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools
- Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment