Sato Y | Micro Device Division Hitachi Ltd.:(present Address)semiconductor Technology Academic Research Cente
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- 同名の論文著者
- Micro Device Division Hitachi Ltd.:(present Address)semiconductor Technology Academic Research Centeの論文著者
Micro Device Division Hitachi Ltd.:(present Address)semiconductor Technology Academic Research Cente | 論文
- Deterministic Built-in Test for Logic Circuits Having Multiple Clocks
- High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model(Special Issue on Test and Verification of VLSI)
- A MINIMIZATION METHOD FOR COMPUTING PARAMETER BOUNDS IN AN INTERVAL VALUED LINEAR REGRESSION MODEL USING INTERVAL ANALYSIS(Theory and Applications)
- Multidimensional Global Optimization Using Interval Slopes(Numerical Analysis and Optimization)
- Application of High Quality Built-in Test Using Neighborhood Pattern Generator to Industrial Designs(Test)(VLSI Design and CAD Algorithms)