Jung Keechul | Soongsil Univ. Seoul Kor

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Soongsil Univ. Seoul Kor | 論文

• A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
• A Precision Floating-Gate Mismatch Measurement Technique for Analog Application(Session 7B : Si IC and Circuit Technology)
• A Precision Floating-Gate Mismatch Measurement Technique for Analog Application(Session 7B : Si IC and Circuit Technology)
• A Physical-Based Modeling for Accurate Wide-Width LDMOS(Session 7B : Si IC and Circuit Technology)
• A Physical-Based Modeling for Accurate Wide-Width LDMOS(Session 7B : Si IC and Circuit Technology)

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