Murata Shigeharu | Device Development Center Hitachi Ltd.
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概要
関連著者
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Murata Shigeharu
Device Development Center, Hitachi, Ltd.
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Murata Shigeharu
Device Development Center Hitachi Ltd.
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丹波 展雄
日立製作所デバイス開発センタ
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Ikeda Tokihiro
Atomic Phys. Lab. Riken
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Hiramoto Toshirou
Device Development Center Hitachi Ltd.
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Yoshida Makoto
the Device Development Center, Hitachi Ltd.
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Hiramoto Toshiro
the Device Development Center, Hitachi Ltd.
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Fujiwara Tsuyoshi
the Device Development Center, Hitachi Ltd.
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Hashimoto Takashi
the Device Development Center, Hitachi Ltd.
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Muraya Tetsuya
the Device Development Center, Hitachi Ltd.
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Murata Shigeharu
the Device Development Center, Hitachi Ltd.
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Watanabe Kunihiko
the Device Development Center, Hitachi Ltd.
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Tamba Nobuo
the Device Development Center, Hitachi Ltd.
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Ikeda Takahide
the Device Development Center, Hitachi Ltd.
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Tamba Nobuo
The Device Development Center Hitachi Ltd.
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Usami M
Hitachi Ltd. Kokubunji‐shi Jpn
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Iwabuchi Masato
Device Development Center, Hitachi, Ltd.
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Usami Masami
Device Development Center, Hitachi, Ltd.
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Kashiyama Masamori
General Purpose Computer Division, Hitachi, Ltd.
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Oomori Takashi
General Purpose Computer Division, Hitachi, Ltd.
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Hiramoto Toshiro
Device Development Center, Hitachi, Ltd.
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Hashimoto Takashi
Device Development Center, Hitachi, Ltd.
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Nakajima Yasuhiro
Hitachi Computer Engineering Co., Ltd.
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Oomori Takashi
General Purpose Computer Division Hitachi Ltd.
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Iwabuchi Masato
Device Development Center Hitachi Ltd.
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Watanabe Kunihiko
The Device Development Center Hitachi Ltd.
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Fujiwara Tsuyoshi
The Device Development Center Hitachi Ltd.
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Muraya Tetsuya
The Device Development Center Hitachi Ltd.
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Kashiyama Masamori
General Purpose Computer Division Hitachi Ltd.
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Nakajima Yasuhiro
Hitachi Computer Engineering Co. Ltd.
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Yoshida Makoto
The Device Development Center Hitachi Ltd.
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Hashimoto Takashi
Device Development Center Hitachi Ltd.
著作論文
- A Bipolar-Based 0.5μm BiCMOS Technology on Bonded SOI for High-Speed LSIs (Special Section on High Speed and High Density Multi Functional LSI Memories)
- A 1.5-ns Cycle-Time 18-kb Pseudo-Dual-Port RAM with 9K Logic Gates (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))