Yeo Yee-chia | Silicon Nano Device Lab Dept. Of Ece National University Of Singapore (nus)
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Silicon Nano Device Lab Dept. Of Ece National University Of Singapore (nus) | 論文
- A Physics-based Compact Model for I-MOS Transistors
- A Double-Gate Tunneling Field-Effect Transistor with Silicon-Germanium Source for High-Performance, Low Standby Power, and Low Power Technology Applications
- Device Design and Scalability of a Double-Gate Tunneling Field-Effect Transistor with Silicon–Germanium Source
- Silicon Strain-Transfer-Layer (STL) and Graded Source/Drain Stressors for Enhancing the Performance of Silicon-Germanium Channel P-MOSFETs
- N-channel MOSFETs with In-situ Silane-Passivated Gallium Arsenide Channel and CMOS-Compatible Palladium-Germanium Contacts