KWONG D.-L. | Dept. of ECE, University of Texas
スポンサーリンク
概要
関連著者
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KWONG D.-L.
Dept. of ECE, University of Texas
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Kwong D.-l.
Dept. Of Ece University Of Texas
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Joo Moon
Silicon Nano Device Lab (sndl) Department Of Electrical And Computer Engineering National University
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Cho Byung
Silicon Nano Device Lab (sndl) Department Of Electrical And Computer Engineering National University
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BALASUBRAMANIAN N.
Institute of Microelectronics
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KWONG D.-L.
Institute of Microelectronics
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Joo Moon
Silicon Nano Device Laboratory Dept. Of Electrical & Computer Engineering Nus
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CHI D.
Institute of Materials Research & Engineering
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CHAN D.
Silicon Nano Device Lab., Dept of Electrical and Computer Engineering, National University of Singap
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Wang Y.
Institute of microelectronics, Department of Electrical Engineering, National Cheng-Kung University
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Wang Y.
Institute Of Microelectronics
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WANG X.
SNDL, ECE Dept, National University of Singapore
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YU H.
IMEC
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KWONG D-L
Institute of Microelectronics
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KANG J.
Institute of Microelectronics, Peking University
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REN C.
Silicon Nano Device Lab, Dept. of ECE, National University of Singapore
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YU H.
Silicon Nano Device Lab, Dept. of ECE, National University of Singapore
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WANG X.
Silicon Nano Device Lab, Dept. of ECE, National University of Singapore
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LI M-F.
Silicon Nano Device Lab, Dept. of ECE, National University of Singapore
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YEO Y-C.
Silicon Nano Device Lab, Dept. of ECE, National University of Singapore
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Li M-f.
Sndl Ece Dept National University Of Singapore
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Yeo Y-c.
Silicon Nano Device Lab Dept. Of Ece National University Of Singapore
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Cho Byung
Silicon Nano Device Laboratory Dept. Of Electrical & Computer Engineering Nus
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Wang X.
Sndl Ece Dept National University Of Singapore
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Kang J.
Institute Of Microelectronics Peking University
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Wang Y.
Institute Of Microelectronics Peking University
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Wang Y.
Institute Of Materials Science And Engineering ; Center For Nanoscience And Nanotechnology National
著作論文
- Behavior of Effective Work Function in Metal/High-K Gate Stack under High Temperature Process
- A Novel Dual-Metal Gate Integration Process for Sub-1nm EOT HfO_2 CMOS Devices