Choi H‐y | School Of Electrical & Computer Eng. Chungbuk National University
スポンサーリンク
概要
関連著者
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Lee D‐i
Gwangju Inst. Of Sci. And Technol. Kor
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Choi H‐y
School Of Electrical & Computer Eng. Chungbuk National University
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Lee Dong-ik
Department Of Information And Communications Gwangju Institute Of Science And Technology
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KIM Soo-Hyun
Department of Information and Communications, Gwangju Institute of Science and Technology
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CHOI Ho-Yong
School of Electrical & Computer Eng., Chungbuk National University
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Kim Soo-hyun
Department Of Information And Communications Gwangju Institute Of Science And Technology
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Oh Eunjung
Department Of Information And Communications Kwang-ju Institute Of Science & Technology (k-jist)
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Kim Soo-hyun
Department Of Hospital Infection Control Korea University Hospital
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Lee Jeong-gun
The Department Of Information And Communications Gwangju Institute Of Science And Technology
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Lee Jeong-gun
The Department Of Information And Communications Kwang-ju Institute Of Science & Technology(k-ji
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OH Eunjung
the Department of Information and Communications, Kwang-Ju Institute of Science & Technology(K-JIST)
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LEE Dong-Ik
the Department of Information and Communications, Kwang-Ju Institute of Science & Technology(K-JIST)
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CHOI Ho-Yong
the School of Electrical & Electronics Engineering, Chungbuk National University
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Lee Dong-ik
The Department Of Info.& Comm. K-jist
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KIM Kiseon
Department of Information and Communications, Gwangju Institute of Science and Technology
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OH Eunjung
Department of Information and Communications, Kwang-Ju Institute of Science & Technology (K-JIST)
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Lee D‐i
Department Of Information And Communications Gwangju Institute Of Science And Technology
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Kim Kiseon
Department Of Information And Communications Gwangju Institute Of Science And Technology
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Kim Kiseon
Department Of Information And Communication At The Gwangju Institute Of Science And Technology (gist
著作論文
- Test Generation for SI Asynchronous Circuits with Undetectable Faults from Signal Transition Graph Specification(Special Section on Papers Selected from ITC-CSCC 2000)
- Synthesis for Testability of Synchronous Sequential Circuits with Strong-Connectivity Using Undefined States on State Transition Graph(Test)(VLSI Design and CAD Algorithms)
- High-Level Test Generation for Asynchronous Circuits from Signal Transition Graph(Special Section on VLSI Design and CAD Algorithms)