IWATA Kenichi | Renesas Electronics Corporation
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概要
Renesas Electronics Corporation | 論文
- Design Choice in 45-nm Dual-Port SRAM — 8T, 10T Single End, and 10T Differential
- 招待講演 A 65nm embedded SRAM with wafer level burn-in mode, leak-bit redundancy and E-trim fuse for known good die (集積回路)
- Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration
- A Low-Power Microcontroller with Body-Tied SOI Technology(Low-Power System LSI, IP and Related Technologies)
- A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology