Khanh Nguen | VLSI Design and Education Center (VDEC), The University of Tokyo
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VLSI Design and Education Center (VDEC), The University of Tokyo | 論文
- A 8bit two stage time-to-digital converter using time difference amplifier
- Time Difference Amplifier with Robust Gain Using Closed-Loop Control
- Time Difference Amplifier with Robust Gain Using Closed-Loop Control
- C-12-67 Digital Substrate Noise Canceling Method using Active Guard Ring
- A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment