Kim Yu | Memory R&D Division, Hynix Semiconductor Inc., Ichon P.O. Box 1010, Ichon-si, Kyoungki-do 467-701, Korea
スポンサーリンク
概要
- 同名の論文著者
- Memory R&D Division, Hynix Semiconductor Inc., Ichon P.O. Box 1010, Ichon-si, Kyoungki-do 467-701, Koreaの論文著者
Memory R&D Division, Hynix Semiconductor Inc., Ichon P.O. Box 1010, Ichon-si, Kyoungki-do 467-701, Korea | 論文
- Effect of Selective Oxidation Conditions on Defect Generation in Gate Oxide
- Gate Oxide Reliability Characterization of Tungsten Polymetal Gate with Low-Contact-Resistive WSix/WN Diffusion Barrier in Memory Devices
- Characteristics of Multiple Thickness Gate Oxides Using Oxidation Enhancement by Si Implantation
- Diffusion Barrier Characteristics of TiSix/TiN for Tungsten Dual Poly Gate in DRAM
- Roles of Ti, TiN, and WN as an Interdiffusion Barrier for Tungsten Dual Polygate Stack in Memory Devices