IKEDA Makoto | The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC)
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- The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC)の論文著者
The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC) | 論文
- Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme in SOI Technology
- Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
- On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
- On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction