Impact of Source/Drain Junction and Cell Shape on Random Telegraph Noise in NAND Flash Memory

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概要

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• A comprehensive numerical study of threshold voltage fluctuation (\Delta V_{\text{T}}) in scaled NAND flash memory caused by random telegraph noise (RTN) and discrete dopant fluctuation (RDF) in both the channel and the cell-to-cell space [source/drain (S/D)] region was carried out. Following a three-dimensional (3D) Monte Carlo (MC) procedure, the statistical distribution of \Delta V_{\text{T}} is estimated, considering the effects of both the random placement of discrete doping atoms and a discrete single trap at the tunnel oxide/substrate interface. The result demonstrates the significant influence of the doping in the S/D regions. For the cells with and without an S/D junction, the electron concentration in the S/D region is determined by the pass voltage of the unselected cell (V_{\text{pass}}) and the neighboring cell V_{\text{T}} (V_{\text{T(n)}}), owing to the fringing fields of neighboring floating gates (FGs). As a result, \Delta V_{\text{T}} increases in the S/D region as V_{\text{pass}} - V_{\text{T(n)}} decreases. The fluctuation amplitude strongly depends on the [single-trap RTN] position along the cell length (L) and width (W) directions. For the cell shape with rounding of the active area (AA) at the shallow trench isolation (STI) edge, the results indicate that the high \Delta V_{\text{T}} area moves from the AA edge towards the center area along the W-direction.

• 2013-07-25

著者

• Li Fu-Hai

  Institute of Communications Engineering, National Chiao Tung University, Hsinchu 300, Taiwan

• Shirota Riichiro

  Institute of Communications Engineering, National Chiao Tung University, Hsinchu 300, Taiwan

関連論文

• Study Trapped Charge Distribution in P-Channel Silicon--Oxide--Nitride--Oxide--Silicon Memory Device Using Dynamic Programming Scheme
• Impact of Source/Drain Junction and Cell Shape on Random Telegraph Noise in NAND Flash Memory

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