Optimal Channel Ion Implantation for High Memory Margin of Capacitor-Less Memory Cell Fabricated on Fully Depleted Silicon-on-Insulator
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概要
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The effect of channel doping concentration on the memory margin of capacitor-less (Cap-less) memory cells fabricated on fully depleted silicon-on-insulator (SOI) n-metal–oxide–semiconductor field-effect transistors (MOSFETs) was investigated. It was observed that the memory margin of Cap-less memory cells is significantly varied by the channel doping concentration, i.e., it increases with doping concentrations up to $1.4 \times 10^{17}$ cm-3 and then decreases with higher doping concentrations. In particular, at a concentration of $1.4 \times 10^{17}$ cm-3 it increased 1.8 times compared with that at $1.5 \times 10^{15}$ cm-3. This gives rise to speculation that the memory margin of Cap-less memory cells fabricated on fully depleted SOI n-MOSFETs can be increased by enlarging the lateral electric field and can be decreased by reducing the current density. These results suggest that a higher memory margin in Cap-less memory cells can be obtained by optimizing channel doping concentration in fully depleted SOI n-MOSFETs.
- 2010-03-25
著者
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Jung-Mi Oh
Advanced Semiconductor Material and Device Development Center, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea
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Kim Seong-Je
Advanced Semiconductor Material and Device Development Center, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea
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Oh Jung-Mi
Advanced Semiconductor Material and Device Development Center, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea
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Shim Tae-Hun
Advanced Semiconductor Material and Device Development Center, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea
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Jea-Gun Park
Advanced Semiconductor Material and Device Development Center, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea
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Tae-Hun Shim
Advanced Semiconductor Material and Device Development Center, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea
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Seong-Je Kim
Advanced Semiconductor Material and Device Development Center, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul 133-791, Republic of Korea
関連論文
- Optimal Channel Ion Implantation for High Memory Margin of Capacitor-Less Memory Cell Fabricated on Fully Depleted Silicon-on-Insulator
- Effects of Bulk Microdefects and Metallic Impurities on p–n Junction Leakage Currents in Silicon