A Direct Observation of the Distributions of Local Trapped-Charges and the Interface-States near the Drain Region of the Silicon–Oxide–Nitride–Oxide–Silicon Device for Reliable Four-Bit/Cell Operations

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This paper reports the direct observation of the threshold voltage shifts with trapped-charge densities as well as the interface-state densities after $10^{4}$ program/erase (P/E) cycles at each state of the four levels in the drain edge of the silicon–oxide–nitride–oxide–silicon (SONOS) structure. We prepared a SONOS device with a 3.4-nm-thick tunnel oxide, showing 2-bit and 4-level operations at program voltages of 4–6 V, with a 10-year retention and $10^{4}$ P/E endurance properties. Then, by using charge pumping methods, we observed the vertical and the lateral distributions of the trapped-charges and their interface-states with the gate biases at each level of the four states in the drain edge. The trapped-charges densities at the “10”, “01”, and “00” states in the drain region were estimated to be $1.4\times 10^{12}$, $3.0\times 10^{12}$, and $4.9\times 10^{12}$ cm-2, respectively, with a lateral width of 220 nm. The peak location of the interface-state density was shifted from the drain edge to the channel with an increase in the gate bias. These observations will be quite useful to optimize the program conditions for reliable 4-bit/cell SONOS operations.
2010-11-25