Dual-Gate Polycrystalline Silicon Thin-Film Transistors with Intermediate Lightly Doped Region

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概要

• 論文の詳細を見る

• I have proposed and developed dual-gate polycrystalline silicon thin-film transistors (poly-Si TFTs) with an intermediate lightly doped region (LDR) for the reduction of leakage current. The proposed poly-Si TFTs are easily fabricated and have a symmetric structure less sensitive to misalignment than the conventional LDD poly-Si TFTs. In the proposed TFTs, it is proved that a decrease in leakage current is due to a reduction in lateral electric field at the drain edge and a reduction in on-current is caused by an increase in the resistance of the LDR. The leakage current of the proposed TFTs is significantly reduced and the maximum ON/OFF current ratio is obtained with a 2 μm LDR length and a $2\times 10^{13}$/cm2 LDR implant dose.

• 2006-08-15

著者

• Chung Hoon-ju

  School Of Electronic Engineering Kumoh National Institute Of Technology

• Chung Hoon-Ju

  School of Electronic Engineering, Kumoh National Institute of Technology, 1 Yangho-dong, Gumi, Gyeongbuk 730-701, Korea

関連論文

• Dual-Gate Polycrystalline Silicon Thin-Film Transistors with Intermediate Lightly Doped Region
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• Driving Method Compensating for the Hysteresis of Polycrystalline Silicon Thin-Film Transistors for Active-Matrix Organic Light-Emitting Diode Displays

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