Interface-Trap-Assisted Emission in Si Complementary Metal–Oxide–Semiconductor Light-Emitting Devices

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概要

• 論文の詳細を見る

• A metal–oxide–semiconductor (MOS) structure or a forward-biased $ pn$ junction with an interdigitated structure has been investigated for light-emitting devices using the standard Si complementary metal-oxide-semiconductor (CMOS) process. Current hysteresis is observed to be associated with the reduction of light emission in the MOS structure. An oxide trap level of $1.1\pm 0.1$ eV is found and contributes to Frenkel–Poole conduction in the high-current region. Furthermore, traps at the interface between silicon and oxide are believed to be responsible for light emission in both MOS structure and $ pn$ junction diodes.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2005-06-15

著者

• Liu Cheng-kuang

  Department Of Electronic Engineering National Taiwan University Of Science And Technology

• Lee Shyh-cheng

  Department Of Electronic Engineering National Taiwan University Of Science And Technology

• Lee Hsiu-chih

  Department Of Electronic Engineering National Taiwan University Of Science And Technology

• Lin Yi-Pen

  Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan 106, R.O.C.

• Lee Hsiu-Chih

  Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan 106, R.O.C.

関連論文

• Interface-Trap-Assisted Emission in Si Complementary Metal–Oxide–Semiconductor Light-Emitting Devices

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