A Novel Sensing Circuit for High Speed Synchronous Magneto-Resistive RAM

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概要

• 論文の詳細を見る

• A novel sensing scheme for a magneto-resistive random access memory (MRAM) with a twin cell structure is presented. New sensing circuit has very simple structure while providing stable operation. Voltage-controlled transistor switch limits the voltage across the magnetic tunnel junction (MTJ) under 400 mV while reading. The circuit layout is small enough to fit into 4-cell pitches that high speed synchronous operation is made possible in MRAMs as in DRAMs or SRAMs. We have fully integrated a 256 bit synchronous MRAM operating at 100 MHz with 0.35 μm complementary metal oxide semiconductor (CMOS) technology.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2004-04-15

著者

• Lee Seungjun

  Ewha Womans University, Dept. of Information Electronics Engineering, Daehyun-Dong, Seodaemun-Gu, Seoul 120-750, Korea

• Shin Hyungsoon

  Ewha Womans University, Dept. of Information Electronics Engineering, Daehyun-Dong, Seodaemun-Gu, Seoul 120-750, Korea

• Lee Seungyeon

  Ewha Womans University, Dept. of Information Electronics Engineering, Daehyun-Dong, Seodaemun-Gu, Seoul 120-750, Korea

• Kim Hyejin

  Ewha Womans University, Dept. of Information Electronics Engineering, Daehyun-Dong, Seodaemun-Gu, Seoul 120-750, Korea

• Kim Daejung

  Kookmin University, Dept. of Electronics Engineering, 861-1 Chongnung-dong, Songbuk-gu, Seoul, 136-702, Korea

関連論文

• A Novel Sensing Circuit for High Speed Synchronous Magneto-Resistive RAM

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