Suppression of Anomalous Edge Channel Effect for 0.15 μm DRAM Cell and Beyond

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概要

• 論文の詳細を見る

• Dynamic random access memory (DRAM) cell for suppressing the anomalous threshold voltage (VT) lowering due to interlayer dielectric (ILD)-related edge channel effect has been intensively investigated. Our work verifies that anomalous edge channel effect is mainly responsible for the migration of ILD-contained residual hydrogen and moisture (H2O) into Si/SiO2. Thus, the cell structure to cut off migration path is suggested, which enables to realize the robust characteristics of retention time, regardless of the variation of ILD-related process integration in 0.15 μm-DRAM.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2003-04-15

著者

• Choi Se-kyeong

  Memory R&d Division Hynix Semiconductor Inc.

• Choi Se-Kyeong

  Memory R&D Division, Hynix Semiconductor Inc., 1 Hyangjeong-dong Heungduk-gu, Cheongju Chungbuk 361-725, Korea

• Kim l-Gweon

  Memory R&D Division, Hynix Semiconductor Inc., 1 Hyangjeong-dong Heungduk-gu, Cheongju Chungbuk 361-725, Korea

• Park Joo-Seong

  Memory R&D Division, Hynix Semiconductor Inc., 1 Hyangjeong-dong Heungduk-gu, Cheongju Chungbuk 361-725, Korea

関連論文

• Suppression of Anomalous Edge Channel Effect for 0.15μm DRAM Cell and Beyond
• Suppression of Anomalous Edge Channel Effect for 0.15 μm DRAM Cell and Beyond

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