Analysis of Leakage Current in Cu/SiO2/Si/Al Capacitors under Bias-Temperature Stress

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概要

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• An investigation was carried out of the conduction mechanism by which leakage current arises in Cu/SiO2/Si/Al capacitors under bias-temperature (BT) stress. $C$–$V$ measurements on the capacitors before and after BT stress revealed that the stress reduces the capacitance of the Si depletion layer and induces the formation of interface states at the SiO2/Si interface. Secondary ion mass spectroscopy (SIMS) measurements on samples after BT stress showed the presence of Cu not only in the oxide, but also at the SiO2/Si interface. These results indicate that BT stress causes Cu ions to drift through the SiO2 film as far as the Si substrate. The good linearity of the $\ln(I/E)$ versus $E^{1/2}$ curve suggests that current conduction is due to Poole–Frenkel emissions. The origin of the Poole–Frenkel current is also discussed based on a study of how BT stress at a negative bias affects the gate current of the capacitors.

• 2003-10-15

著者

• NISHINO Hirotaka

  Environmentally Benign Process Technology Laboratory, Semiconductor Technology Research Department,

• FUKUDA Takuya

  Environmentally Benign Process Technology Laboratory, Semiconductor Technology Research Department,

• YANAZAWA Hiroshi

  Environmentally Benign Process Technology Laboratory, Semiconductor Technology Research Department,

• Matsunaga Hironori

  Environmentally Benign Process Technology Laboratory Semiconductor Technology Research Department As

• Yanazawa Hiroshi

  Environmentally Benign Process Technology Laboratory, Semiconductor Technology Research Department, Association of Super-Advanced Electronics Technologies (ASET), 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa 244-0817, Japan

• Matsunaga Hironori

  Environmentally Benign Process Technology Laboratory, Semiconductor Technology Research Department, Association of Super-Advanced Electronics Technologies (ASET), 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa 244-0817, Japan

• Nishino Hirotaka

  Environmentally Benign Process Technology Laboratory, Semiconductor Technology Research Department, Association of Super-Advanced Electronics Technologies (ASET), 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa 244-0817, Japan

関連論文

• Analysis of Leakage Current in Cu/SiO_2/Si/Al Capacitors under Bias-Temperature Stress
• Analysis of Leakage Current in Cu/SiO2/Si/Al Capacitors under Bias-Temperature Stress

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