Merged DRAM with Logic/Analog (MDLA) Technology for Single-Chip Solution

概要

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This paper describes a process integration of Merged DRAM (dynamic random access memory) with Logic and Analog (MDLA) using high performance 0.35 µm CMOS technology for the implementation of "System on a Chip". DRAM whose cell size was 2.1 µm2 and analog cores were embedded in 0.35 µm logic chip without sacrifice of transistor performance of logic circuitry. The obtained values of Idsaturation of NMOS/PMOS transistors were about 530 and 250 µA/µm at 3.3 V, respectively. Dual gate oxide process was developed to support 5 V operation as well as 3.3 V operation. The key process feature of this study was that the aluminum alloy layer was used as a bit line in DRAM cells on the contrary to the employment of polycide in the conventional DRAM technology. In this study, metal-insulator-metal (MIM) capacitor scheme was employed for the applications in high-resolution analog cores. The low value of voltage coefficient of capacitance as low as 10 ppm/V could be achieved with MIM scheme.
INSTITUTE OF PURE AND APPLIED PHYSICSの論文
1999-04-30