Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders

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概要

• 論文の詳細を見る

• The throughput rate of Viterbi decoding (VD) is not limited by the speed of functional units when look-ahead computation techniques are used. The disadvantages of the look-ahead computation in VD are the hardware complexity and the decode latency. In this paper, implementation methods of the look-ahead ACS computation are proposed to improve the hardware efficiency and reduce the latency where the hardware efficiency and the latency can be balanced with a single parameter.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• Ito Kazuhito

  Graduate School Of Science And Engineering Saitama University

• SHIRASAKA Ryoto

  Graduate School of Science and Engineering, Saitama University

関連論文

• A Processor Accelerator for Software Decoding of BCH Codes
• Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors
• A Trace-Back Method with Source States for Viterbi Decoding of Rate-1/n Convolutional Codes
• Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders

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