A Processor Accelerator for Software Decoding of BCH Codes

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概要

• 論文の詳細を見る

• The BCH code is one of the well-known error correction codes and its decoding contains many operations in Galois field. These operations require many instruction steps or large memory area for look-up tables on ordinary processors. While dedicated hardware BCH decoders achieves higher decoding speed than software, the advantage of software decoding is its flexibility to decode BCH codes of variable parameters. In this paper, an auxiliary circuit to be embedded in a pipelined processor is proposed which accelerates software decoding of various BCH codes.

• （社）電子情報通信学会の論文
• 2010-07-01

著者

• Ito Kazuhito

  Graduate School Of Science And Engineering Saitama University

関連論文

• A Processor Accelerator for Software Decoding of BCH Codes
• Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors
• A Trace-Back Method with Source States for Viterbi Decoding of Rate-1/n Convolutional Codes
• Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders

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